1. Field of the Invention
The present invention relates to a lead frame in which more leads are provided in order to increase the number of pins and in which electrical properties and heat radiation are improved, and to a semiconductor device using such a lead frame.
2. Description of the Related Art
FIG. 21 is a plan view of a conventional lead frame, and FIG. 22 is a cross-sectional view taken along line A--A of FIG. 21. In these drawings, numeral 10 denotes a lead frame, and numeral 11 denotes leads each having an outer lead portion 12 and an inner lead portion 13. Numeral 14 denotes a die pad, and number 15 denotes suspending leads suspending the die pad 14 from its four corners. Numeral 16 denotes tie bars connecting the respective leads 11 to the suspending leads 15 so as not to loosen the leads 11. In a frame 17, the tie bars 16 are cut during a manufacturing process for semiconductor devices in order to separate the respective leads 11 from each other. The above components are all supported by the frame 17 which extends outwardly from these components, being formed into the lead frame 10. Typically, a plate is punched by a die, or is chemically etched to form the frame 17 as shown in FIG. 21. In most cases, the surfaces of the die pad 14 and the inner lead portions 13 are plated with silver (Ag), gold (Au), or copper (Cu). The die pad 14 is then pressed downward as shown in FIG. 22.
The structures of the tie bars 16 and the frame 17 are not particularly important in the present invention, so that explanations and drawings of these structures will be omitted hereinafter.
FIG. 23 is a plan view showing the inner structure of a conventional semiconductor device which employs the lead frame 10 in FIG. 21, and FIG. 24 is a cross-sectional view taken along line B-B of FIG. 23. Numeral 20 denotes a semiconductor chip; numeral 21 denotes a large number of electrode pads made of aluminum which are arranged on a surface of the semiconductor chip 20; numeral 30 denotes a die bonding material; and numeral 40 denotes fine metal wires (Au wires). A resin-mold portion 50 resin-molding the semiconductor device is indicated by broken lines.
A manufacturing method for such a semiconductor device will now be described. First, the semiconductor chip 20 is placed on the die pad 14 with the die bonding material 30. A material whose main constituent is solder or an electrically-conductive resin is generally used as the die bonding material 30. Next, heat energy is applied to the top of each Au wire 40 having a diameter of about 30 .mu.m so as to form a metal ball (not shown). The metal ball is pressed against each electrode pad 21 on the heated semiconductor chip 20, while at the same time ultrasonic oscillation is provided. Thus, an intermetalic compound is produced between the metal ball and each electrode pad 21 to join them together. The Au wire 40 is then drawn out and pressed against each inner lead portion 13, while at the same time ultrasonic oscillation is provided. Thus, an intermetalic compound is also produced between the Au wire 40 and each inner lead portion 13 to join them together. The method explained above is referred to as an ultrasonic-thermo-compression bonding method. The thus-formed leads 11 close to the inner lead portions 13 of lead frame 10 and semiconductor chip 20 are all resin-molded as shown by the resin-molding portion 50. The semiconductor device is thus manufactured.
At this stage, when the Au wire 40 is 30 .mu.m in diameter and over 3.0 mm in length for example, the wire looping shape is not stable because it is easy for wire bending and hanging to occur.
Since the conventional semiconductor device is constructed as above, as the number of pins on the semiconductor chip increases, and as the chip design rule is lowered from a standard for 1.3 .mu.m (for one mega byte DRAMs) to a standard for 1.0 .mu.m (for four mega byte DRAMs), and further to a standard for 0.8 .mu.m (for 16 mega byte DRAMs), shrunken electrode pads accordingly are arranged on a smaller semiconductor chip. As a result, the width of the inner lead portions approaches their process limit. For this reason, it becomes impossible to extend the inner lead portions to near the electrode pads. Consequently, the Au wire looping, connecting the inner lead portions to the electrode pads, must be extended far in excess of its optimum length. This causes poor quality of the wire looping, such as bending and hanging, with the result that semiconductor devices cannot be mass-produced stably.